Capacitors are an essential element in integrated circuit technology. They are used, for example, as storage nodes in dynamic random access memories (DRAMS), decoupling elements in fast switching logic chips, and filter elements in signal processing chips. Currently three main capacitor structures are used for the above mentioned applications.
One conventional capacitor structure is a planar capacitor. A typical planar capacitor is fabricated on a substrate, has an insulator layer and a conductive layer, and is known as a thin polysilicon gated capacitor. An example of a planar capacitor is described in U.S. Pat. No. 4,419,812. Formed in either the substrate or the metalization layers, planar capacitors have a drawback because they are essentially two dimensional and occupy a large area of the underlying structure.
Another capacitor structure is the trench capacitor, which is typically fabricated in the substrate. An example of a trench capacitor is described in U.S. Pat. No. 4,958,318. Conventional trench capacitors have several drawbacks. In particular, when formed in the substrate, a trench capacitor uses a significant percentage of the total processing cost and still occupies some critical area thereby decreasing the area available for other devices in the substrate, such as transistors. In addition, trench capacitors may cause dislocations in the substrate.
A third capacitor structure is the stacked capacitor, formed in the first levels of the metalization and insulator stacks. The typical stacked capacitor is formed in the first level of metallurgy and insulation in integrated circuit technology. The topography associated with stacked capacitors aggravates problems associated with forming contacts for these capacitors as well as integrating the capacitor with other connections within the substrate. Furthermore, when stacked capacitors are form ed in the insulation layers above the substrate, although these capacitors may conserve active area in the substrate, this conservation results in an exaggerated three dimensional topography due to the attendant increase in the vertical dimension to achieve the necessary capacitance. Another drawback is that stacked capacitors require extensive processing steps to fabricate.
As shown in FIG. 1, the planar area occupied by capacitor 100 depends on the feature size F and the lithography used to define it. Thus, capacitors of minimum dimension with reduced topography and high capacitance are desired. In addition, it is desired that the size of reduced topography capacitors integrate easily into current device processing.